The present invention relates to algorithmic pattern generators in automatic test equipment for testing memory devices, and more particularly to algorithmic pattern generators useful for testing synchronous semiconductor random access memory devices.
Algorithmic pattern generators (APGs) are well-known components of automatic test equipment for electronic circuits. In one conventional design, the APG is essentially special purpose, very high speed RISC processor having a very long instruction word (VLIW) architecture. In such an architecture, each functional block or arithmetic logic unit (ALU) of the APG has a corresponding set of instruction bits in the APG instruction word. Typically, an APG generates addresses in two parts, X and Y, and thus has an X register and a Y register, each generally wide enough to form half an address for a target memory device. To test a memory addressable by a 32-bit address, for example, X and Y registers of 16 bits each would be sufficient. In addition, an APG typically has a small utility register called the Z register. Each of these registers is subject to manipulation by APG instructions.
Memory testers must test memories having a number of challenging operating modes. In a burst mode of operation, a memory uses an internal address generating means to generate addresses for itself in response to a clock signal. From a start address, words of data are read from, or written to, the memory up to the burst length, which is programmable by setting a register in the memory. A typical set of selectable values is 1 (no burst), 2, 4, and 8 words per burst.
In burst mode, an addressing mode (or wrap type) of either "sequential" or "interleaved" specifies the order in which the burst data will be addressed. The interleaved mode is also known as Intel addressing mode. The addressing mode may be programmed by setting a register in the memory. To illustrate addressing mode operation, in the sequential mode, for a burst length of 8, the low order 3 bits of the starting address are incremented modulo 8 through eight addresses before the next higher address bit is incremented, while the interleave mode, the low order 3 bits of the address are formed as the exclusive or (XOR) of the starting address low order 3 bits and a counter counting from zero to 7. With a starting address having low order starting bits 010 (binary), the low order 3 bits of the interleave address sequence are 2, 3, 0, 1, 6, 7, 4, and 5 (decimal).